The conventional method for manufacturing low-temperature polysilicon N-type thin film transistor is to form N+ region (i.e. heavily-doping region) and N− region (N− region is also called LDD: light drain doping) after crystallizing and patterning the polysilicon. The conventional method needs to define the N+ region and N− region respectively by using two masks, and implant the phosphorus ions twice. Then, a gate insulating layer is deposited by plasma enhanced chemical vapor deposition. The conventional method for manufacturing a low-temperature polysilicon N-type thin film transistor has a complicated process flow and high fabrication cost, and the thickness of the gate layer in the N-type thin film transistor manufactured by the conventional method is uniform and a large leakage current occurs when the thin film transistor is in the off state causes the thin film transistor to be not very sensitive to the turn-off and turn-on, the display effect of the display panel will be affected.